DR8051CPU

Features:

100% software compatible with industry standard 8051
RISC architecture enables to execute instructions 6.7 times faster compared to standard 8051
12 times faster multiplication
9.6 times faster division
Up to 256 bytes of internal (on-chip) Data Memory
Up to 64K bytes of Program Memory
Up to 16M bytes of external (off-chip) Data Memory
User programmable Program Memory Wait States solution for wide range of memorie speed
User programmable External Data Memory Wait States solution for wide range of memories speed
De-multiplexed Address/Data bus to allow easy connection to memory
Interface for additional Special Function Registers
Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states


Description

DR8051CPU is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about low power consumption. Additionally an advanced power management unit makes DR8051CPU core perfect for portable equipment where low power consumption is mandatory.

DR8051CPU soft core is 100% binarycompatible with the industry standard 8051 8- bit microcontroller. There are two configurations of DR8051CPU: Harward where external data and program buses are separated, and von Neumann with common program and external data bus. DR8051CPU has RISC architecture 6.7 times faster compared to standard architecture and executes 65-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty.

DR8051CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.