DP83952

Features:

Compliant with the IEEE 8023 Repeater Specification
13 network connections (ports) per chip
Selectable on-chip twisted-pair transceivers
Cascadable for large hub applications
Compatible with AUI compliant transceivers
On-chip Elasticity Buffer Manchester encoder and decoder
Separate Partition state machines for each port
Compatible with 8023k Hub Management requirements
Provides port status information for LED displays including receive collision partition link status and jabber
Power-up configuration options
Repeater and Partition Specifications Transceiver Interace Status Display Processor Operations
Simple processor interface for repeater management and port disable
On-chip Event Counters and Event Flag Arrays
Serial Management Bus Interface to combine packet and repeater status information
CMOS process for low power dissipation
Single 5V supply

Pinout




Specifications

SupplyVoltage(V_CC) ......................................-0.5Vto7.0V
DCInputVoltage(V_IN) ...........................-0.5VtoV_CC +0.5V
DCOutputVoltage(V_OUT) ......................-0.5VtoV_CC+ 0.5V
StorageTemperatureRange(T_STG) ...............-65to150
PowerDissipation(P_D)................................................. 2W
LeadTemperature
    (Soldering10sec)................................................ 260
ESD Rating
    (R_zap= 15kC_zap =120pF)....................................1500V


Description

The DP83952 RIC II Repeater Interface Controller is an''Enhanced'' version of the DP83950 RIC RIC II is fully backward pin and functional compatible with the RIC The DP83952 RIC II has the same basic architecture as the RIC with additional feature enhancements RIC II provides addi-
tional network security options additional statistics for repeater activities and a faster processor interface When DP83952 RIC II is used in a ''non-secure'' mode it functions in the same manner as the DP83950 RIC When RIC II is used in a''secure'' mode it restricts unauthorized nodes from intrud-ing andor eavesdropping into the network The DP83952 RIC II utilizes internal CAMs to storecompare addresses of valid nodes when network
security is desired

DP83952 RIC II implements the IEEE 8023 multiport repeater unit specifications It is fully compliant with the 8023 repeater specification for the repeater segment partition and jabber lockup protection state machines

The DP83952 RIC II repeater design consists of two major functional blocks Segment Specific Block and Shared Functional Blocks The Segment Specific Block implements the IEEE repeater requirements on a per network port basiswhilethe Shared Functional Blocks implement the core logic blocks for the IEEE repeater unit The Shared Functional Blocks consist of repeater receive multiplexor an on chip phase lock loop (PLL) decoder for Manchester data an Elasticity Buffer for preamble regeneration transmit encoder and de-multiplexor for Manchester data

The DP83952 RIC II can be connected up to 13 cable seg- ments via its network interface ports One port is fully AUI compatible and is able to connect to an external MAU using the maximum length of AUI cable The other 12 ports have integrated 10BASE-T transceivers These transceiver functions may be bypassed so that the RIC II may be used with external transceivers such as the DP8392 coaxial trans- ceivers

A large repeater unit can be constructed by cascading DP83952 RIC IIs together via the Inter-RIC^TM bus All the cascaded RIC IIs form a single repeater unit

The DP83952 RIC II is configurable for specific applications It pro- vides port status information for LED array displays and a simple interface for system processors The DP83952 RIC II possess-es multi-function counters and status flag arrays to facilitatenetwork statistics gathering A serial Hub Management In-
terface is available for the collection of data in Managed Hub applications