Features: ·32-bit non-multiplexed address and data bus·High-speed, interruptible DMA·Linked-list buffer management maximizes flexibility·Two independent 32-byte transmit and receive FIFOs·Bus compatibility for all standard microprocessors·Supports big and little endian formats·Integrated IEEE 802....
DP83932C-33: Features: ·32-bit non-multiplexed address and data bus·High-speed, interruptible DMA·Linked-list buffer management maximizes flexibility·Two independent 32-byte transmit and receive FIFOs·Bus compat...
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Features: ·16 10/100/1000 Mb/s Ethernet ports with non-blocking wire-speed performance·32 Gbit/s i...
The SONIC (Systems-Oriented Network Interface Controller) is a second-generation Ethernet Controller designed to meet the demands of today's high-speed 32- and 16-bit systems. Its system interface operates with a high speed DMA that typically consumes less than 3% of the bus bandwidth (25 MHz bus clock). Selectable bus modes provide both big and little endian byte ordering and a clean interface to standard microprocessors. The linked-list buffer management system of DP83932C-33 offers maximum flexibility in a variety of environments from PC-oriented adapters to high-speed motherboard designs. Furthermore, the DP83932C-33 integrates a fully-compatible IEEE 802.3 Encoder/Decoder (ENDEC) allowing for a simple 2-chip solution for Ethernet when the SONIC is paired with the DP8392 Coaxial Transceiver Interface or a 10BASE-T transceiver.
For increased performance, the DP83932C-33 implements a unique buffer management scheme to efficiently process, receive and transmit packets in system memory. No intermediate packet copy is necessary. The DP83932C-33 buffer management uses three areas in memory for (1) allocating additional resources, (2) indicating status information, and (3) buffering packet data. During reception, the DP83932C-33 stores packets in the buffer area, then indicates receive status and control information in the descriptor area. The system allocates more memory resources to the DP83932C-33 by adding descriptors to the memory resource area. The transmit buffer management uses two areas in memory: one for indicating status and control information and the other for fetching packet data. The system can create a transmit queue allowing multiple packets to be transmitted from a single transmit command. The packet data can reside on any arbitrary byte boundary and can exist in several non-contiguous locations.