DP83865

Features: · Ultra low power consumption typically 1.1 watt· Fully compliant with IEEE 802.3 10BASE-T, 100BASETX and 1000BASE-T specifications· Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12· 3.3 V or 2.5 V MAC interfaces:· IEEE 802...

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SeekIC No. : 004327966 Detail

DP83865: Features: · Ultra low power consumption typically 1.1 watt· Fully compliant with IEEE 802.3 10BASE-T, 100BASETX and 1000BASE-T specifications· Integrated PMD sublayer featuring adaptive equalization...

floor Price/Ceiling Price

Part Number:
DP83865
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/20

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Product Details

Description



Features:

· Ultra low power consumption typically 1.1 watt
· Fully compliant with IEEE 802.3 10BASE-T, 100BASETX and 1000BASE-T specifications
· Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
· 3.3 V or 2.5 V MAC interfaces:
· IEEE 802.3u MII
· IEEE 802.3z GMII
· RGMII version 1.3
· User programmable GMII pin ordering
· IEEE 802.3u Auto-Negotiation and Parallel Detection
· Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
· Speed Fallback mode to achieve quality link
· Cable length estimator
· LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
· Supports 25 MHz operation with crystal or oscillator.
· Requires only two power supplies, 1.8 V (core and analog) and 2.5 V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
· User programable interrupt
· Supports Auto-MDIX at 10, 100 and 1000 Mb/s
· Supports JTAG (IEEE1149.1)
· 128-pin PQFP package (14mm x 20mm)





Application

· 10/100/1000 Mb/s capable node cards
· Switches with 10/100/1000 Mb/s capable ports
·High speed uplink ports (backbone)





Pinout

  Connection Diagram




Specifications

Supply Voltage IO_VDD -0.4V to 4.2 V
Supply Voltage CORE_VDD,-0.4V to 2.4V
1V8_AVDD1, 1V8_AVDD2
Supply Voltage 2V5_AVDD1, -0.4V to 3.6V
2V5_AVDD2
Input Voltage (DCIN) -0.5V to IO_VDD + 0.5V
Output Voltage (DCOUT) -0.5V to IO_VDD + 0.5V
Storage Temperature -65°C to 150°C
ESD Protection 6000V





Description

The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOStechnology, fabricated at National Semiconductor's South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.




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