DM74S112

This DM74S112 device contains two independent negative-edge-trig-gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip- flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs of DM74S112 as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs of DM74S112 regardless of the logic levels of the other inputs.