DM74LS190

Features: *ounts 8-4-2-1 BCD or binary*Single downup count control line*Count enable control input*Ripple clock output for cascading*Asynchronously presettable with load control*Parallel outputs*Cascadable for n-bit applications*Average propagation delay 20 ns*Typical clock frequency 25 MHz*Typica...

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SeekIC No. : 004327221 Detail

DM74LS190: Features: *ounts 8-4-2-1 BCD or binary*Single downup count control line*Count enable control input*Ripple clock output for cascading*Asynchronously presettable with load control*Parallel outputs*Cas...

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Part Number:
DM74LS190
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

*ounts 8-4-2-1 BCD or binary
*Single downup count control line
*Count enable control input
*Ripple clock output for cascading
*Asynchronously presettable with load control
*Parallel outputs
*Cascadable for n-bit applications
*Average propagation delay 20 ns
*Typical clock frequency 25 MHz
*Typical power dissipation 100 mW



Specifications

If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications
SupplyVoltage                                                               7V
InputVoltage                                                                 7V
Operating Free Air Temperature Range
DM54LS                                                    -55  to +125
DM74LS                                                         0  to +70
StorageTemperatureRange                     -65  to +150



Description

These  LS191 circuits are synchronous reversible updown coun-ters The  LS191  is a 4-bit binary counter and the LS190 is a BCD counter ynchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock)counters

The outputs of the LS191   four master-slave flip-flops are triggered on a low-to-high level transition of the clock input if the enable input is low A high at the enable input inhibits count-ing Level changes at either the enable input or the down up input should be made only when the clock input is high The direction of the count is determined by the level of the downup input When low the counter counts up and when
high it counts down

These LS191  counters are fully programmable that is the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs The output will change independent of the level of the clock in-put This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs

The clock downup and load inputs are buffered to lower the drive requirement which significantly reduces the num-ber of clock drivers etc required for long parallel words. Two outputs of  LS191  have been made available to perform the cas-cading function ripple clock and maximumminimum count The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when anoverflow or underflow condition exists The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used or to the clock input if parallel enabling is used The maximumminimum count output can be used to accom-plish look-ahead for high-speed operation




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