DM74LS165

The DM74LS165 is an 8-bit serial shift register which shifts datain the direction of QA toward QH when clocked. Parallel-inaccess is made available by eight individual direct datainputs, which are enabled by a low level at the shift/loadinput. These registers also feature gated clock inputs andcomplementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, permittingone input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking,and holding either clock input LOW with the load inputHIGH enables the other clock input. The clock-inhibit inputshould be changed to the high level only while the clockinput is HIGH. Parallel loading of DM74LS165 is inhibited as long as theload input is HIGH. Data at the parallel inputs are loadeddirectly into the register on a HIGH-to-LOW transition of theshift/load input, regardless of the logic levels on the clock,clock inhibit, or serial inputs.