DM74AS873NT

Low Level Output Current :
Polarity : Non-Inverting
Number of Output Lines : 3
Supply Voltage - Max : 5.5 V
Packaging : Tube
Supply Voltage - Min : 4.5 V
Logic Type : D-Type Transparent Latch
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
Number of Circuits : 2
Package / Case : PDIP-24
High Level Output Current : - 15 mA
Logic Family : 74AS
Propagation Delay Time : 6.5 ns at 4.5 V to 5.5 V


Features:

·  Switching specifications at 50 pF
·  Switching specifications guaranteed over full temperature
   and VCC range
·  Advanced oxide-isolated, ion-implanted Schottky TTL process
·  3-STATE buffer-type outputs drive bus lines directly
·  Space Saving 300 Mil Wide Package
·  Bus structured pinout


Pinout




Specifications

Supply Voltage ..........................................................7V
Input Voltage............................................................ 7V
Voltage Applied to Disabled Output .......................5.5V
Operating Free Air Temperature Range... 0°C to +70°C
Storage Temperature Range ..............-65°C to +150°C
Typical qJA
N Package .....................................................47.0°C/W
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation


Description

These DM74AS873NT dual 4-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive of DM74AS873NT  provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the DM74AS873 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control of DM74AS873NT does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

The pinout of DM74AS873NT is arranged to ease printed circuit board layout. All data inputs are on one side of the package while all outputs are on the other side.