Bus Transceivers Oct Bus Tran and Reg
DM74AS651WM: Bus Transceivers Oct Bus Tran and Reg
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Logic Type : | Bipolar | Logic Family : | 74AS | ||
Number of Channels per Chip : | 8 | Input Level : | TTL | ||
Output Level : | TTL | Output Type : | 3-State | ||
High Level Output Current : | - 15 mA | Low Level Output Current : | 48 mA | ||
Propagation Delay Time : | 9 ns | Supply Voltage - Max : | 5.5 V | ||
Supply Voltage - Min : | 4.5 V | Maximum Operating Temperature : | + 70 C | ||
Package / Case : | SOIC-24 | Packaging : | Tube |
This DM74AS651WM device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.
This DM74AS651WM bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. DM74AS651WM is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The registers in the DM74AS646, DM74AS648 are edgetriggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored. The SAB and SBA control pins of DM74AS651WM are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a "make before break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.
The enable G and direction control pins of DM74AS651WM provide four modes of operation; real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal store data transfer to bus A or B.When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled.