DM74AS648NT

Number of Channels per Chip : 8
Output Type : 3-State
Low Level Output Current : 48 mA
Maximum Operating Temperature : + 70 C
Packaging : Tube
Supply Voltage - Max : 5.5 V
Supply Voltage - Min : 4.5 V
Logic Type : Bipolar
Input Level : TTL
Output Level : TTL
High Level Output Current : - 15 mA
Package / Case : PDIP-24
Propagation Delay Time : 9 ns
Logic Family : 74AS


Features:

·  Switching specifications at 50 pF
·  Switching specifications guaranteed over full temperature and VCC range
·  Advanced oxide-isolated, ion-implanted Schottky TTL process
·  Functionally and pin-for-pin compatible with LS TTL counterpart
·  3-STATE buffer-type outputs drive bus lines direct


Pinout




Specifications

Supply Voltage ...........................................................7V
Input Voltage
Control Inputs ............................................................7V
I/O Ports ..................................................................5.5V
Operating Free Air Temperature Range..... 0°C to +70°C
Storage Temperature Range ................-65°C to +150°C
Typical qJA
N Package ........................................................41.1°C/W
M Package ........................................................81.5°C/W
Note 3: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation 


Description

This DM74AS648NT incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.

This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. It is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
 
The registers in the DM74AS646, DM74AS648 are edgetriggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored.

The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a "make before break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.

The enable G and direction control pins provide four modes of operation; real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal store data transfer to bus A or B.

When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled.