DM74AS373N

Low Level Output Current :
Number of Circuits : 8
Polarity : Non-Inverting
Number of Output Lines : 3
Supply Voltage - Max : 5.5 V
Package / Case : PDIP-20
Packaging : Tube
Supply Voltage - Min : 4.5 V
Logic Type : D-Type Transparent Latch
Maximum Operating Temperature : + 70 C
Minimum Operating Temperature : 0 C
High Level Output Current : - 15 mA
Propagation Delay Time : 6 ns at 4.5 V to 5.5 V
Logic Family : 74AS


Features:

·  Switching specifications at 50 pF
·  Switching specifications guaranteed over full temperature
   and VCC range
·  Advanced oxide-isolated, ion-implanted Schottky TTL process
·  Functionally and pin for pin compatible with LS and ALS
   TTL counterparts
·  Improved AC performance over LS and ALS TTL counterparts
·  3-STATE buffer-type outputs drive bus lines directly


Pinout




Specifications

Supply Voltage ............................................................7V
Input Voltage ..............................................................7V
Voltage Applied to Disabled Output......................... 5.5V
Operating Free Air Temperature Range ....0°C to +70°C
Storage Temperature Range ...............-65°C to +150°C
Typical qJA
N Package ......................................................52.5°C/W
M Package...................................................... 70.5°C/W
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.


Description

These 8-bit registers feature totem-pole 3-STATE outputs,DM74AS373N designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these DM74AS373N registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the DM74AS373N are transparent Dtype latches, meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.

A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high impedance state. In the high-impedance state the outputs of DM74AS373N neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs of DM74AS373N are OFF.