DM74AS161

Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to , 70°C
Storage Temperature Range -65°C to , 150°C
Typical JA
N Package 71.5°C/W
M Package 101.0°C/W

Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions for actual device operation.

These synchronous presettable counters feature an inter nal carry look ahead for application in high speed counting designs. The DM74AS161 and DM74AS163 are 4-bi binary counters. The DM74AS161 clear asynchronously while the DM74AS163 clear synchronously. The carry out put is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs
change coincident with each other when so instructed by count enable inputs and internal gating. This mode of oper ation eliminates the output counting spikes which are nor mally associated with asynchronous (ripple clock counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input wave form.

These DM74AS161 counters are fully programmable, that is, the outputs may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on the clock or enable inputs.

The DM74AS161 clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. This counter is provided with a clear on power-up feature. The DM74AS163 clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all LOW outputs. LOW-to-HIGH transitions at the clear input of the DM74AS163 is also permissible regardless of the levels of logic on the clock, enable or load inputs.

The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs (P and T) and a ripple carry output. Both count-enable inputs must be HIGH to count. The T input is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cas- caded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74AS161 and DM74AS163, may occur regardless of the logic level on the clock.

The DM74AS161 and DM74AS163 feature a fully independent clock circuit. Changes made to control inputs (enable P or T, or load) that will modify the operating mode will have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times.