DM74ALS564AWM

Mounting Style : SMD/SMT
Supply Voltage - Max : 5.5 V
Input Type : Single-Ended
Output Type : Single-Ended
Low Level Output Current : 24 mA
Packaging : Tube
Number of Circuits : 8
Logic Family : 74ALS
Maximum Operating Temperature : + 70 C
Package / Case : SOIC-20
Logic Type : D-Type Edge Triggered Flip-Flop
Polarity : Inverting
Propagation Delay Time : 14 ns
High Level Output Current : - 2.6 mA


Features:

·  Switching specifications at 50 pF
·  Switching specifications guaranteed over full temperature and VCC range
·  Advanced oxide-isolated, ion-implanted Schottky TTL process
·  3-STATE buffer-type outputs drive bus lines directly


Pinout




Specifications

Supply Voltage ..........................................................7V
Input Voltage ............................................................7V
Voltage Applied to Disabled Output .......................5.5V
Operating Free Air Temperature Range ...0°C to +70°C
Storage Temperature Range ..............-65°C to +150°C
Typical qJA
N Package ......................................................56.0°C/W
M Package ......................................................75.0°C/W
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.


Description

These DM74ALS564AWM 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the DM74ALS564AWM are edge-triggered inverting D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the complement of the logic states that were set up at the D inputs.

A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs of DM74ALS564AWM neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs of DM74ALS564AWM are OFF.