Features: Complementary outputsDirect overriding load (data) inputsGated clock inputsParallel-to-serial data conversionSpecificationsSupply Voltage 7VInput Voltage 7VOperating Free Air Temperature Range 0 to , 70Storage Temperature Range -65 to , 150Typical JAN Package 74.0/WM Package 104.0/W No...
DM74ALS165: Features: Complementary outputsDirect overriding load (data) inputsGated clock inputsParallel-to-serial data conversionSpecificationsSupply Voltage 7VInput Voltage 7VOperating Free Air Temperature R...
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Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0 to , 70
Storage Temperature Range -65 to , 150
Typical JA
N Package 74.0/W
M Package 104.0/W
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The "Recommended Operating Conditions" table will define the conditions for actual device operation.
The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit func-tion and a complemented serial output, QH.
Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accom-plish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the DM74ALS165 register are enabled while SH/LD is LOW indepen-dently of the levels of CLK, CLK INH, or SER inputs.