DM7490A

Typical power dissipation
    90A 145 mW
    93A 130 mW
Count frequency 42 MHz

  Each of these DM7490A monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the 90A and divide-by-eight for the 93A

  All of these DM7490A counters have a gated zero reset and the 90A also has gated set-to-nine inputs for use in BCD nine's com-plement applications

  To use their maximum count length (decade or four-bit bina-ry) the B input is connected to the Q_A output The input count pulses are applied to input A and the outputs are as described in the appropriate truth table A symmetrical di-vide-by-ten count can be obtained from the DM7490A counters by connecting the Q_D output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output Q_A