DM7485

Features: *Typical power dissipation 275 mW*Typical delay (4-bit words) 23 ns*Alternate Military/Aerospace device (5485) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.PinoutSpecificationsSupply Voltage ......................................................

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DM7485 Picture
SeekIC No. : 004327069 Detail

DM7485: Features: *Typical power dissipation 275 mW*Typical delay (4-bit words) 23 ns*Alternate Military/Aerospace device (5485) is available. Contact a National Semiconductor Sales Office/Distributor for s...

floor Price/Ceiling Price

Part Number:
DM7485
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

* Typical power dissipation 275 mW
* Typical delay (4-bit words) 23 ns
* Alternate Military/Aerospace device (5485) is available.
   Contact a National Semiconductor Sales Office/Distributor
   for specifications.




Pinout

  Connection Diagram


Specifications

Supply Voltage ..............................................................................7V
Input Voltage .............................................................................5.5V
Operating Free Air Temperature Range
DM54 and 54 ............................................................-55 to +125
DM74 .............................................................................0 to +70
Storage Temperature Range ....................................-65 to +150



Description

These  4-bit magnitude comparators DM7485 perform comparison of straight binary or BCD codes. Three fully-decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. These DM7485 are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A  B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A e B input. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words.




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