Features: ` Parallel inputs and outputs` Four operating modes: -Synchronous parallel load -Right shift -Left shift -Do nothing` Positive edge-triggered clocking` Direct overriding clear` Typical clock frequency 105 MHz` Typical power dissipation 425 mWSpecificationsSupply Voltage ....................
DM54S194: Features: ` Parallel inputs and outputs` Four operating modes: -Synchronous parallel load -Right shift -Left shift -Do nothing` Positive edge-triggered clocking` Direct overriding clear` Typical clo...
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Supply Voltage ..........................................................................7V
Input Voltage .........................................................................5.5V
Operating Free Air Temperature Range DM54S ..-550C to +1250C
DM74S .....................................................................00C to +700C
Storage Temperature Range ..............................-650C to +1500C
Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.
These DM54S194 bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-modecontrol inputs, and a direct overriding clear line. The DM54S194 register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing)
Synchronous parallel loading of DM54S194 is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flipflops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right of DM54S194 is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.
Clocking of the flip-flop is inhibited when both mode control inputs are low.