DM54LS85

Features: Typical power dissipation 52 mWTypical delay (4-bit words) 24 nsAlternate Military/Aerospace device (54LS85) is available.Contact a National Semiconductor Sales Office/Distributor for specifications.SpecificationsSupply Voltage 7VInput Voltage 7VOperating Free Air Temperature RangeDM54LS...

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SeekIC No. : 004327003 Detail

DM54LS85: Features: Typical power dissipation 52 mWTypical delay (4-bit words) 24 nsAlternate Military/Aerospace device (54LS85) is available.Contact a National Semiconductor Sales Office/Distributor for spec...

floor Price/Ceiling Price

Part Number:
DM54LS85
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 Typical power dissipation 52 mW
 Typical delay (4-bit words) 24 ns
 Alternate Military/Aerospace device (54LS85) is available.Contact a National Semiconductor Sales Office/Distributor for specifications.


Specifications

Supply Voltage                                                                              7V
Input Voltage                                                                                7V
Operating Free Air Temperature Range
DM54LS and 54LS                                                   -55 to +125
DM74LS                                                                        0 to +70
Storage Temperature Range                                  -65 to +150



Description

   These DM54LS85 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three outputs. These DM54LS85 devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A l B, A k B, and A e B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits.

   The stage handling the least-significant bits must have a high-level voltage applied to the A e B input. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words.



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