DM54LS365A

Features: *Alternate Military/Aerospace device (54LS365A) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications.PinoutSpecificationsSupply Voltage .............................................................................7VInput Voltage .......................

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DM54LS365A Picture
SeekIC No. : 004326992 Detail

DM54LS365A: Features: *Alternate Military/Aerospace device (54LS365A) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications.PinoutSpecificationsSupply Voltage ................

floor Price/Ceiling Price

Part Number:
DM54LS365A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/18

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Product Details

Description



Features:

* Alternate Military/Aerospace device (54LS365A) is
   available. Contact a National Semiconductor Sales Office/
   Distributor for specifications.



Pinout

  Connection Diagram


Specifications

Supply Voltage .............................................................................7V
Input Voltage ...............................................................................7V
Operating Free Air Temperature Range
   DM54LS and 54LS ...............................................-55 to a125
   DM74LS ......................................................................0 to a70
Storage Temperature Range ..................................-65 to a150



Description

This DM54LS365A device contains six independent gates each of which performs a non-inverting buffer function. The outputs of DM54LS365A have the TRI-STATE feature. When enabled, the outputs of DM54LS365A exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.




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