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DM54LS323

Features: Common I/O for reduced pin count Four operation modes: shift left, shift right, parallel load and store Separate continuous inputs and outputs from Q0 and Q7 allow easy cascading Fully synchronous reset TRI-STATE outputs for bus oriented applicationsPinoutSpecificationsIf Military/Aerosp...

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DM54LS323: Features: Common I/O for reduced pin count Four operation modes: shift left, shift right, parallel load and store Separate continuous inputs and outputs from Q0 and Q7 allow easy cascading Fully syn...

DM54LS323 Data Sheet

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Part Number:
DM54LS323
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

 Common I/O for reduced pin count
Four operation modes: shift left, shift right, parallel load and store
Separate continuous inputs and outputs from Q0 and Q7 allow easy cascading
Fully synchronous reset
TRI-STATE outputs for bus oriented applications


Pinout

Connection Diagram


Specifications

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage                                                           7V
Input Voltage                                                             7V
Operating Free Air Temperature Range
   DM54LS                                                -55to +125
   DM74LS                                                     0to +70
Storage Temperature Range                   -65to +150


Description

The DM54LS323 is an 8-bit universal shift/storage register with TRI-STATEÉ outputs. The function of DM54LS323  is similar to the 'LS299 with the exception of Synchronous Reset. Parallel load in-puts and flip-flop outputs are multiplexed to minimize pin count. Separate inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right, and parallel load. All modes are activated on the LOW-to-HIGH transition of the Clock.




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