DM54LS299

Features: · Common I/O for reduced pin count· Four operation modes: shift left, shift right, load and store· Separate shift right serial input and shift left serial input for easy cascading· TRI-STATE outputs for bus oriented applicationsPinoutSpecificationsSupply Voltage ............................

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DM54LS299 Picture
SeekIC No. : 004326989 Detail

DM54LS299: Features: · Common I/O for reduced pin count· Four operation modes: shift left, shift right, load and store· Separate shift right serial input and shift left serial input for easy cascading· TRI-STA...

floor Price/Ceiling Price

Part Number:
DM54LS299
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

· Common I/O for reduced pin count
· Four operation modes: shift left, shift right, load and store
· Separate shift right serial input and shift left serial input for easy cascading
· TRI-STATE outputs for bus oriented applications



Pinout

  Connection Diagram


Specifications

Supply Voltage .........................................................................7V
Input Voltage ...........................................................................7V
Operating Free Air Temperature Range DM54 ...-550C to +1250C
DM74LS ..................................................................00C to +700C
Storage Temperature Range .............................-650C to a1500C

Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.




Description

The DM54LS299 is an 8-bit universal shift/storage register with TRI-STATE. outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register.




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