DM54LS138

Features: *Designed specifically for high speed: Memory decoders Data transmission systems* LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception* LS139 contains two fully independent 2-to-4-line decoders/ demultiplexers* Schottky clamped for high perf...

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SeekIC No. : 004326960 Detail

DM54LS138: Features: *Designed specifically for high speed: Memory decoders Data transmission systems* LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception* LS139...

floor Price/Ceiling Price

Part Number:
DM54LS138
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

* Designed specifically for high speed:
   Memory decoders
   Data transmission systems
* LS138 3-to-8-line decoders incorporates 3 enable inputs
   to simplify cascading and/or data reception
* LS139 contains two fully independent 2-to-4-line decoders/
   demultiplexers
* Schottky clamped for high performance
* Typical propagation delay (3 levels of logic)
   LS138 21 ns
   LS139 21 ns
* Typical power dissipation
   LS138 32 mW
   LS139 34 mW
* Alternate Military/Aerospace devices (54LS138,
   54LS139) are available. Contact a National Semiconductor
   Sales Office/Distributor for specifications.



Pinout

  Connection Diagram


Specifications

Supply Voltage ....................................................................................7V
Input Voltage ......................................................................................7V
Operating Free Air Temperature Range
   DM54LS and 54LS ......................................................-55 to +125
   DM74LS .............................................................................0 to +70
Storage Temperature Range .........................................-65 to +150



Description

These DM54LS138 Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these DM54LS138 decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these DM54LS138 decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The DM54LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The DM54LS139 comprises two separate two-line-to-four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications.

All of these DM54LS138 decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.




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