DM54LS107A

  This DM54LS107A device contains two independent negative-edge-trig-gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs may change while the clock is high or low without affecting the outputs of DM54LS107A as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs of DM54LS107A regardless of the logic levels of the other inputs