DM54191

Features:

* Single down/up count control line
* Count enable control input
* Ripple clock output for cascading
* Asynchronously presettable with load control
* Parallel outputs
* Cascadable for n-bit applications
* Alternate Military/Aerospace device (54191) is available.
   Contact a National Semiconductor Sales Office/
   Distributor for specifications.

 

Specifications

Supply Voltage                                                     7V
Input Voltage                                                    5.5V
Operating Free Air Temperature Range
DM54 and 54                                     -55to+125
DM74                                                     0 to+70
Storage Temperature Range            -65 to+150


Description

  This DM54191 circuit is a synchronous, reversible, up/down counter.The DM54191 is a 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
  The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input, if the enable input is low. A high at the enable input inhibits counting. Level changes at either the enable input or the down/ up input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter counts up and when high, it counts down.
  This DM54191 counter is fully programmable; that is, the outputs of DM54191 may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words.
  Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the DM54191 counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The DM54191 counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking issused, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.