DLKPC192S Selling Leads, Price trend, DLKPC192S DataSheet download, circuit diagram from SeekIC.com

Features: 10-Gbps Ethernet LAN PCS With 64b/66b ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS Technology IEEE 802.3 Management Data Interface (MDIO) Advanced 0.18-m CMOS Technology Less Than 1.5 W Power Consumption...

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SeekIC No. : 004326817 Detail

DLKPC192S: Features: 10-Gbps Ethernet LAN PCS With 64b/66b ENDEC 10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology 10-Gbps 16-Bit Interface (XSBI) Using LVDS Technology IEEE 802....

DLKPC192S Data Sheet

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Part Number:: DLKPC192S
Supply Ability:: 5000

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1~5000

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Product Details

Description

Features:

10-Gbps Ethernet LAN PCS With 64b/66b ENDEC
10-Gbps Media-Independent Interface (XGMII) Using 2.5-V SSTL Class 2 Technology
10-Gbps 16-Bit Interface (XSBI) Using LVDS Technology
IEEE 802.3 Management Data Interface (MDIO)
Advanced 0.18-m CMOS Technology
Less Than 1.5 W Power Consumption
Low-Cost 289-Ball PBGA Package

Specifications

Supply voltage range, V_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 2.4 V
I/O supply voltage range: VDDS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V
VDDO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V
Voltage on any SSTL input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDO+0.5 V
Voltage on any SSTL output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDO+0.5 V
Voltage on any LVDS input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDS+0.5 V
Voltage on any LVDS output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDS+0.5 V
Voltage on any LVTTL input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDS+0.5 V
Voltage on any LVTTL output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDS+0.5 V
Electrostatic discharge (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:2 kV
Case temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 55°C to 125°C
Junction temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C to 150°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
2. This rating is measured using MIL-STD-883C Method, 3015.7.

Description

The DLKPC192S performs all physical coding sublayer (PCS) functions for proposed IEEE 802.3ae/D2.0 10-Gbps Ethernet serial network (LAN) connections.

The DLKPC192S connects to the media access control (MAC) and all higher layers of the OSI protocol stack via the 10-Gbps media independent interface (XGMII). The XGMII consists of two unidirectional buses, each with 36 information bits (32 data bits, 4 control bits) plus a clock. The XGMII interface is implemented using 2.5-V, SSTL Class 2 technology. The DLKPC192S connects to physical media via the 10-Gbps 16-bit interface (XSBI). The XSBI bus consists of two unidirectional buses, each with 16 data bits plus a clock. The XSBI interface is implemented utilizing low-voltage differential signaling (LVDS) technology. The DLKPC192S encodes and decodes data using the 64b/66b coding algorithm and provides clock tolerance compensation when needed.

The DLKPC192S can be used in systems where printed-circuit board (PCB) traces between the media access control device and the serializer/deserializer device are sufficiently short, as shown in Figure 1.

Systems requiring PCB traces longer than 6 inches can be implemented by using the TLK3114SA XGMII external sublayer device to increase the allowable PCB trace length to greater than 20 inches, as shown in Figure 2.

DLKPC192S

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