Features: • Standard 8-Bit, 25 MHz UTOPIA Level 1 Link-Layer (Master) Interface Complies with the ATM Forum UTOPIA Specification, Level 1 Version 2.01 (af-phy- 0017.000)• Separate Tx and Rx Clocks and Interface Pins • Supports Cell-Level Handshake for 53- or 54-byte ATM Cells wit...
CoreU1LL: Features: • Standard 8-Bit, 25 MHz UTOPIA Level 1 Link-Layer (Master) Interface Complies with the ATM Forum UTOPIA Specification, Level 1 Version 2.01 (af-phy- 0017.000)• Separate Tx and...
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• Standard 8-Bit, 25 MHz UTOPIA Level 1 Link-Layer (Master) Interface Complies with the ATM Forum UTOPIA Specification, Level 1 Version 2.01 (af-phy- 0017.000)
• Separate Tx and Rx Clocks and Interface Pins • Supports Cell-Level Handshake for 53- or 54-byte ATM Cells with Automatic Add/Drop of the UDF2 Field in the ATM Header in 53-byte Mode
• 16-Bit (54-byte) User Interfaces can be Used Directly or Bolt-Up to One of Actel's ATM Cell Buffer Blocks: ATMBUFx
CoreU1LL is a UTOPIA Level 1 Link-Layer (Master) interface core that connects directly to any ATM PHYLayer (Slave) device and user logic (or optional ATM cell buffer blocks) to provide an interface between the PHYLayer device and a non-standard Link-Layer device or user logic (Figure 1).