Core1553BRT-EBR

• Supports Enhanced Bit Rate 1553
• 10 Mbps Time-Multiplexed Serial Data Bus
• Interfaces to External RAM or Directly to Backend Device
• Synchronous or Asynchronous Backend Interface
• Encoders and Decoders Operate off 100 MHz Clock
• Protocol Control and Memory Interface Operates off 50 MHz Clock
• Interfaces to Standard RS485 Transceivers
• Programmable Mode Code and Sub-Address Legality for Illegal Command Support
• Memory Address Mapping Allowing Emulation of Legacy Remote Terminals
• Fail-Safe State Machines
• Fully Synchronous Operation

Core1553BRT-EBR provides a complete, dual-redundant 1553 enhanced bit rate (EBR) remote terminal (RT) apart from the transceivers required to interface to the bus. A typical system implementation using the Core1553BRT-EBR is shown in Figure 1 and Figure 2 on page 3.

At a high level, Core1553BRT-EBR simply provides a set of memory mapped sub-addresses that "receive data written to" or "transmit data read from." The core can be configured to directly connect to synchronous or asynchronous memory devices. Alternately, the core can directly connect to the backend devices, removing the need for the memory buffers. If memory is used, the core requires 2,048 words of memory, which can be shared with the local CPU.

The core supports all 1553EBR mode codes and allows the user to designate as illegal any mode code or any particular sub-address for both transmit and receive operations. Core1553BRT-EBR command legalization can be done within the core or in an external command legality block via the command legalization interface.