CYM1465A

Features: • 4.5V5.5V operation• CMOS SRAM for optimum speed and power• Low active power (165 mW max.)• Low standby power (L Version)-(110 W max)• 2V data retention (L Version)• JEDEC-compatible pinout• 32-pin, 0.6-inch-wide DIP package• TTL-compatibl...

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CYM1465A Picture
SeekIC No. : 004320630 Detail

CYM1465A: Features: • 4.5V5.5V operation• CMOS SRAM for optimum speed and power• Low active power (165 mW max.)• Low standby power (L Version)-(110 W max)• 2V data retention (L V...

floor Price/Ceiling Price

Part Number:
CYM1465A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 4.5V5.5V operation
• CMOS SRAM for optimum speed and power
• Low active power (165 mW max.)
• Low standby power (L Version)-(110 W max)
• 2V data retention (L Version)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs



Pinout

  Connection Diagram


Specifications

(Above which the useful life may be impaired.)
Storage Temperature .................................55°C to +150°C
Ambient Temperature with
Power Applied............................................... 10°C to +85°C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage .............................................-0.5V to +7.0V



Description

The CYM1465A is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW Output Enable (OE), and three-state drivers. The CYM1465A has an automatic power-down feature that reduces power consumption by more than 99% when deselected.

Writing to the SRAM is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the CYM1465A is then written into the memory location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip select (CE) and output enable (OE) LOW while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appropriate data input/output pins (I/O0 through I/O7).The eight input/ output pins (I/O0 through I/O7) are placed in a high impedance state when the CYM1465A is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).

The CYM1465A is available in a 32-pin 600-mil wide body PDIP package.




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