Position: Home  > All Categories> Integrated Circuits (ICs) > CY7C68000

CY7C68000

Features: .UTMI-compliant/USB-2.0-certified for device operation.Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second.Serial-to-parallel and parallel-to-serial conversions.8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirec-tional external data ...

product image

CY7C68000 Picture
See larger image
SeekIC No. : 004320514 Detail

CY7C68000: Features: .UTMI-compliant/USB-2.0-certified for device operation.Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second.Serial-to-parallel and parallel-to-s...

CY7C68000 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
CY7C68000
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/12/21

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

. UTMI-compliant/USB-2.0-certified for device operation
. Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second
. Serial-to-parallel and parallel-to-serial conversions
. 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirec-tional external data interface 
. Synchronous field and EOP detection on receive pack-ets
. Synchronous field and EOP generation on transmit packets
. Data and clock recovery from the USB serial stream
. Bit stuffing/unstuffing; bit stuff error detection
. Staging register to manage data rate variation due to bit stuffing/unstuffing
. 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
. Ability to switch between FS and HS terminations and signaling
. Supports detection of USB reset, suspend, and resume
. Supports HS identification and detection as defined by the USB 2.0 Specification
. Supports transmission of resume signaling
. 3.3V operation
. Two package options-56-pin QFN, and 56-pin SSOP
. All required terminations, including 1.5K-ohm pull-up on DPLUS, are internal to chip
. Supports USB 2.0 test modes.



Application

. DSL modems
. ATA interface
. Memory card readers
. Legacy conversion devices
. Cameras
. Scanners
. Home PNA
. Wireless LAN
. MP3 players
. Networking.


Pinout

Connection Diagram Connection Diagram


Specifications

Storage Temperature ...........................................65°C to +150°C
Ambient Temperature with Power Supplied.................0°C to +70°C
Supply Voltage to Ground Potential.............................0.5V to +4.0V
DC Input Voltage to Any Input Pin............................................ 5.25 V
DC Voltage Applied to Outputs in High-Z State...0.5V to VCC + 0.5V
Power Dissipation....................................................................630 mW
Static Discharge Voltage.........................................................> 2000V
Max Output Current, per IO pin.................................................. 4 mA
Max Output Current, all 21IO pins .........................................84 mA


Description

The Cypress EZ-USB TX2(TM),CY7C68000 is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial/deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The TX2,CY7C68000 provides a high-speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth. This allows the system designer to keep the complex high- speed analog USB components external to the digital ASIC which decreases development time and associated risk. A standard interface of the CY7C68000 is provided that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface (UTMI) speci- fication version 1.05 dated 3/29/01.

Two packages of the CY7C68000 are defined for the family: 56-pin SSOP and 56-pin QFN.

The function block diagram is shown in Figure 1-1.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Filters
PICO2205A
PICO2204A
Cables, Wires - Management
NM-SF50+
CCK26.5-MM-190-30
Memory Cards, Modules
WT32
VTL5C7
Undefined Category
VI-B63-IU
X27 589
Circuit Protection
A50QS75-4Y
F-17*77
Boxes, Enclosures, Racks
ACLSN12
ACLJIC
View more