CY7C4806V25

CMOS Synchronous (clocked) FIFO memories, CY7C480XV25 meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of the clock on either port by the enable signal. The clocks for each port are independent of one another and can be asynchronous or coincident. The enable for each port is arranged to provide a simple unidirectional interface between microprocessors and/or buses with synchronous control.

Two kinds of reset are available on the CY7C480XV25: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big Endian or Little Endian byte arrangement, selects the CY standard or First-Word Fall-Through (FWFT) mode, and determines the configuration of the programmable flags. The flags can be programmed either in serial mode or in parallel mode. The FIFO also comes with three possible default flag offset settings: 8, 16, or 64. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings.

The CY7C480XV25 have two modes of operation: CY Standard Mode or First-Word Fall-Through Mode (FWFT). In the CY Standard Mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the FWFT Mode, the first long-word (80-bit-wide) written to an empty FIFO appears automatically on the outputs, and no read operation is required. Nevertheless, accessing subsequent words does necessitate a formal read request. FWFT mode is primarily used for cascading 2 or more FIFOs.

The CY7C480XV25 has an EF_OR flag on port B and FF_IR flag on Port A. The EF and FF functions are selected in the CY Standard Mode. EF indicates whether or not the FIFO memory is empty. FF shows whether or not the memory is full. The IR and OR functions are selected in the First-Word Fall-Through mode. IR indicates whether or not the FIFO has memory locations available. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs.

The FIFO has a programmable Almost Empty flag (AE) and a programmable Almost Full flag (AF). AE indicates the number of words left in the FIFO memory is at the user-defined amount. AF indicates the number of words written into the FIFO memory has achieved a predetermined amount. FF_IR and AF flags are synchronized to port A clock that writes data into its array. EF_OR and AE flags are synchronized to Port B clock that reads data from its array. Programmable offsets for AE and AF are loaded in parallel via Port A or in serial via the SD input. The Serial Programming Mode pin (SPM) makes this selection. Three default offsets setting are also provided. The AE threshold can be set at 8, 16 or 64 locations from the empty boundary and AF threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS₀ and FS₁ inputs during Master Reset.

Two or more devices may be used in parallel to create wider data paths. If, at any time, the CY7C480XV25 is not actively performing a function, the chip will automatically power down. During the Power-Down state, supply current consumption (I_CC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power-Down state.

The CY7C480XV25 FIFOs are characterized for operation from 0°C to 70°C commercial, and from 40°C to 85°C industrial.