CY7C441

The CY7C441 and CY7C443 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both the CY7C441 and CY7C443  are 9 bits wide. The CY7C441 has a 512 word by 9 bit memory array, while the CY7C443 has a 2048 word by 9 bit memory array. These devices provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Both the CY7C441 and CY7C443  have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR).

The read (CKR) and write (CKW) clocks of the CY7C441 and CY7C443  may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 83.3 MHz are acceptable.

The CY7C441 and CY7C443 clocked FIFOs provide two status flag pins (F1 and F2). These flags of the CY7C441 and CY7C443 are decoded to determine one of four states: Empty, Almost Empty, Intermediate, and Almost Full (Table 1). The flags are synchronous; i.e., change state relative to either the read clock (CKR) or the write clock (CKW). The Empty and Almost Empty states are updated exclusively by the CKR while Almost Full is updated exclusively by CKW. The synchronous flag architecture guarantees that the flags maintain their status for some minimum time. The CY7C441 and the CY7C443 use center power and ground for reduced noise. Both configurations are fabricated using an advanced .65mm CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by reliable layout techniques and guard rings.