CY7C43682AV

The CY7C436X2AV is a monolithic, high-speed, low-power, CMOS Bidirectional Synchronous FIFO memory that supports clock frequencies up to 133 MHz and has Read access times as fast as 6 ns. Two independent 1K/4K/16K * 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The CY7C436X2AV is a synchronous (clocked) FIFO, meaning that each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

Communication between each port of  the CY7C436X2AV may bypass the  CY7C436X2AV  via two mailbox registers. The mailbox registers' width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Master Reset initializes the Read and Write pointers to the first location of the memory array, and selects parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. Each FIFO has its own independent Master Reset pin, MRST1 and MRST2.

The CY7C436X2AV has two modes of operation. In CY Standard mode, the first word written to an empty FIFO is deposited into the memory array. A Read operation is required to access that word (along with all other words residing in memory). In the First-Word Fall-Through mode (FWFT), the first word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no Read operation required (nevertheless, accessing subsequent words does necessitate a formal Read request). The state of the FWFT/STAN pin during FIFO operation determines the mode in use.

Each FIFO has a combined Empty/Output Ready flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the CY Standard mode. EF indicates whether the memory is full or not. FF indicates whether the FIFO is full. The IR and OR functions are selected in the First- Word Fall-Through mode. IR indicates whether or not the  CY7C436X2AV  has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs.

Each FIFO has a programmable Almost Empty flag (AEA and AEB) and a programmable Almost Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words written to  the CY7C436X2AV achieve a predetermined "almost empty state." AFA and AFB indicate when a selected number of words written to the memory achieves a predetermined "almost full state."[1] FFA/IRA, FFB/IRB, AFA, and AFB are synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA, and AEB are synchronized to the port clock that reads data from its array. Programmable offset for AEA, AEB, AFA, and AFB are loaded in parallel using Port A. Three default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16, or 64 locations from the empty boundary and AFA and AFB threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider data paths.

The CY7C436X2AV FIFOs are characterized for operation from 0°C 70°C commercial, and from 40°C 85°C industrial. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.