CY7C4275

Features:

• High-speed, low-power, first-in first-out (FIFO) memories
• 32K x 18 (CY7C4275)
• 64K x 18 (CY7C4285)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle times)
• Low power
-I_CC=50 mA
-I_SB = 2 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 68-pin PLCC and 64-pin 10x10 TQFP
• Pin-compatible density upgrade to CY7C42X5 families
• Pin-compatible density upgrade to IDT72205/15/25/35/45 


Pinout




Specifications

(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature .......................................65°C to +150°C
Ambient Temperature with
Power Applied...................................................55°C to +125°C
Supply Voltage to Ground Potential ..................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ..................................................... 0.5V to +7.0V
DC Input Voltage ............................................−0.5V to VCC+0.5V
Output Current into Outputs (LOW).................................... 20 mA
Static Discharge Voltage................................................... >2001V
(per MILSTD883, Method 3015)
Latch-Up Current............................................................ >200 mA


Description

The CY7C4275/85 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. The CY7C4275/85 are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

The CY7C4275/85  have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write enable pin (WEN).

When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO of the CY7C4275/85 on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4275/85 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag features are available on the CY7C4275/85 .

Depth expansion of the CY7C4275/85 is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC.