CY7C4271V

The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. The  CY7C4261/71/81/91V are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. The CY7C4261/71/81/91V provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

The  CY7C4261/71/81/91V have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write-enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1 and WEN2/LD are held active, data is continually written into the FIFO of the  CY7C4261/71/81/91V  on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and two read enable pins (REN1, REN2). In addition,the CY7C4261/71/81/91V has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.