CY7C4221V

High-speed, low-power, first-in, first-out (FIFO)  memories
64 x 9 (CY7C4421V)
256 x 9 (CY7C4201V)
512 x 9 (CY7C4211V)
1K x 9 (CY7C4221V)
2K x 9 (CY7C4231V)
4K x 9 (CY7C4241V)
8K x 9 (CY7C4251V)
High-speed 66-MHz operation (15-ns read/write cycle  time)
Low power (I _CC = 20 mA)
3.3V operation for low power consumption and easy  integration into low-voltage systems
5V-tolerant inputs _{VIH max} = 5V

Fully asynchronous and simultaneous read and write operation
Empty, Full, and Programmable Almost Empty and  Almost Full status flags
TTL compatible
Output Enable (OE) pin
Independent read and write enable pins
Center power and ground pins for reduced noise
Width expansion capability
Space saving 32-pin 7 mm * 7 mm TQFP
32-pin PL_CC

(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature  ....................................65°C to +150°C
Ambient Temperature with
Power Applied................................................-55°C to +125°C
Supply Voltage to Ground Potential.......................0.5V to +5.0V
DC Voltage Applied to Outputs
in High-Z State.......................................................0.5V to +5.0V

The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All CY7C4221V are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multi-
processor interfaces, and communications buffering.

The CY7C4221V have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1 , WEN2/LD ).

When WEN1  is LOW and WEN2/LD  is HIGH, data is written into the CY7C4221V on the rising edge of the WCLK signal. While WEN1 , WEN2/LD  is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (WEN1 , REN2 ). In addition, the CY7C42X1V has an Output Enable Pin (OE ). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable.

Depth expansion of CY7C4221V is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.