CY7C371i

Features:

• 32 macrocells in two logic blocks
• 32 I/O pins
• Five dedicated inputs including two clock pins
• In-System Reprogrammable (ISR™) Flash technology
   - JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
   - fMAX = 143 MHz
   - tPD= 8.5 n3s
   - tS = 5 ns
   - tCO = 6 ns
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, and TQFP packages
• Pin-compatible with the CY7C372i


Pinout




Specifications

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature  .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potential .................      −0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State.....................................................   −0.5V to +7.0V
DC Input Voltage .................................................  −0.5V to +7.0V
DC Program Voltage .....................................................        12.5V
Output Current into Outputs (LOW).............................        16 mA
Static Discharge Voltage...........................................        > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................        > 200 mA


Description

The CY7C371i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C371i is designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to high-density CPLDs.

Like all of the UltraLogic™ FLASH370i devices, the CY7C371i is electrically erasable and In-System Reprogrammable (ISR),which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress  ISR function is implemented through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments.

The 32 macrocells of CY7C371i in the CY7C371i are divided between two logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator.

The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource-the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect.

Like all members of the FLASH370i family, the CY7C371i is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371i. In addition, there are three dedicated inputs and two input/clock pins.