Features: • 128 macrocells in 8 LABs• 20 dedicated inputs, up to 64 bidirectional I/O pins• Programmable interconnect array• Advanced 0.65-micron CMOS technology to increase performance• Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFPPinoutSpecifications(Above w...
CY7C346B: Features: • 128 macrocells in 8 LABs• 20 dedicated inputs, up to 64 bidirectional I/O pins• Programmable interconnect array• Advanced 0.65-micron CMOS technology to increase ...
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The CY7C346B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user-configurable, allowing the CY7C346B to accommodate a variety of independent logic functions.
The 128 macrocells in the CY7C346B are divided into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.
Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the chip.
The speed and density of the CY7C346B allow it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C346B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C346B reduces board space, part count, and increases system reliability.