Features: • CMOS for optimum speed/power• Windowed for reprogrammability• High speed -45 ns• Low power -550 mW (commercial) -660 mW (military)• Super low standby power (7C251) -Less than 165 mW when deselected -Fast access: 50 ns• EPROM technology 100% programma...
CY7C251: Features: • CMOS for optimum speed/power• Windowed for reprogrammability• High speed -45 ns• Low power -550 mW (commercial) -660 mW (military)• Super low standby power ...
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• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-45 ns
• Low power
-550 mW (commercial)
-660 mW (military)
• Super low standby power (7C251)
-Less than 165 mW when deselected
-Fast access: 50 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
The CY7C251 and CY7C254 are high-performance 16,384-word by 8-bit CMOS PROMs. When deselected, the CY7C251 automatically powers down into a low-power stand-by mode. The CY7C251 and CY7C254 is packaged in a 300-mil-wide package. The 7C254 is packaged in a 600-mil-wide package and does not power down when deselected. The 7C251 and 7C254 are available in reprogrammable packages equipped with an erasure window; when exposed to UV light, these PROMs are erased and can then be reprogrammed. The memory cells of CY7C251 and CY7C254 utilize proven EPROM floating gate technology and byte-wide intelligent programming algorithms.
The CY7C251 and CY7C254 are plug-in replacements for bipolar devices and offer the advantages of lower power, superior performance, and high programming yield. The EPROM cell requires only 12.5V for the super voltage, and low current requirements allow for gang programming. The EPROM cells allow each memory location to be tested 100% because each location is written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to guarantee that after customer programming, the product will meet DC and AC specification limits.
Reading is accomplished by placing all four chip selects in their active states. The contents of the memory location addressed by the address lines (A0 A13) will become available on the output lines (O0 O7).