Features: • High speed-10 ns• Fast tDOE• CMOS for optimum speed/power• Low active power-495 mW (max, 10 ns L version)• Low standby power-0.275 mW (max, L version)• 2V data retention ( L version only)• Easy memory expansion with CE and OE features̶...
CY7C199B: Features: • High speed-10 ns• Fast tDOE• CMOS for optimum speed/power• Low active power-495 mW (max, 10 ns L version)• Low standby power-0.275 mW (max, L version)...
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The CY7C199B is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. The CY7C199B has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199B is in the standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) of CY7C199B controls the writing/ reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14).
Reading the CY7C199B is accomplished by selecting the CY7C199B and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.
The input/output pins of CY7C199B remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity.