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CY7C195

Features: • High speed -12 ns• Output enable (OE) feature (7C195 and 7C196)• CMOS for optimum speed/power• Low active power -880 mW• Low standby power -220 mW• TTL-compatible inputs and outputs• Automatic power-down when deselectedSpecifications(Above whic...

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CY7C195: Features: • High speed -12 ns• Output enable (OE) feature (7C195 and 7C196)• CMOS for optimum speed/power• Low active power -880 mW• Low standby power -220 mW• TT...

CY7C195 Data Sheet

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Part Number:
CY7C195
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• High speed
   -12 ns
• Output enable (OE) feature (7C195 and 7C196)
• CMOS for optimum speed/power
• Low active power
   -880 mW
• Low standby power
    -220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. 65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................0.5V to VCC + 0.5V
DC Input Voltage[1].................................0.5V to VCC + 0.5V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA


Description

The CY7C194, CY7C195, and CY7C196 are high-performance CMOS static RAMs organized as 65,536 by 4 bits. Easy memory expansion is provided by active LOW Chip Enable( s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and three-state drivers. The CY7C194, CY7C195, and CY7C196 have an automatic power-down feature, reducing the power consumption by 75% when deselected.

Writing to theCY7C194, CY7C195, and CY7C196 are accomplished when the Chip Enable(s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) and Write Enable (WE) inputs are both LOW. Data on the four input pins (I/O0 through I/O3) is written into the memory location, specified on the address pins (A0 through A15).

Reading CY7C194, CY7C195, and CY7C196 are accomplished by taking the Chip Enable( s) (CE on the CY7C194 and CY7C195, CE1, CE2 on the CY7C196) LOW, while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins.

A die coat is used to ensure alpha immunity.




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