Features: • High speed -12 ns• CMOS for optimum speed/power• Low active power -880 mW• Low standby power -220 mW• TTL-compatible inputs and outputs• Automatic power-down when deselectedPinoutSpecifications(Above which the useful life may be impaired. For user gu...
CY7C192: Features: • High speed -12 ns• CMOS for optimum speed/power• Low active power -880 mW• Low standby power -220 mW• TTL-compatible inputs and outputs• Automatic pow...
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The CY7C192 is a high-performance CMOS static RAM organized as 65,536 x 4 bits with separate I/O. Easy memory expansion is provided by active LOW Chip Enable (CE) and three-state drivers. CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 has an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and write enable (WE) inputs are both LOW.
Data on the four input pins (I0 through I3) of CY7C192 is written into the memory location specified on the address pins (A0 through A15).
Reading the CY7C192 is accomplished by taking the Chip Enable (CE) LOW while the Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins.
The output pins of CY7C192 stay in high-impedance state when Write Enable (WE) is LOW, or Chip Enable (CE) is HIGH.
A die coat is used to insure alpha immunity.