Features: * Separate Independent Read and Write data ports - Supports concurrent transactions* 200-MHz clock for high bandwidth* 2-Word Burst on all accesses* Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz * Two input clocks (K and K) for pr...
CY7C1910BV18: Features: * Separate Independent Read and Write data ports - Supports concurrent transactions* 200-MHz clock for high bandwidth* 2-Word Burst on all accesses* Double Data Rate (DDR) interfaces on bo...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
(Above which the useful life may be impaired.)
Storage Temperature ...........................65°C to +150°C
Ambient Temperature with
Power Applied.........................................10°C to +85°C
Supply Voltage on V DDRelative to GND.......0.5V to +2.9V
DC Voltage Applied to Outputs
in High-Z State..................................0.5V to VDDQ + 0.3V
DC Input Voltage[12] .......................0.5V to VDDQ + 0.3V
Current into Outputs (LOW).......................................20 mA
Static Discharge Voltage........................................ > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR(TM)-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to comp letely eliminate the need to "turn-around" the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are comp letely independent of one another. In order to maximize data throughput, both Read and Write ports of CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 are equipped with Double Data Rate (DDR) interf aces. Each address location is associated with two 8-bit words (CY7C1310BV18) or 9-bit words (CY7C19 10BV18) or 18-bit words (CY7C1312BV18) or 36-bit words (CY7C13 14BV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds."
Depth expansion of CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 are accomplished with Port Selects for each port. Port selects allow each port to operate indep endently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs of CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and CY7C1314BV18 pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.