Features: ·Separate independent read and write data ports ❐ Supports concurrent transactions
·300 MHz to 400 MHz clock for high bandwidth
·4-Word Burst for reducing address bus frequency
·Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 800 MHz) at 400 MHz
·Read latency of 2.5 clock cycles
·Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
·Echo clocks (CQ and CQ) simplify data capture in high speed systems
·Data valid pin (QVLD) to indicate valid data on the output
·Single multiplexed address input bus latches address inputs for both Read and Write Ports
·Separate port selects for depth expansion
·Synchronous internally self-timed writes
·Available in x8, x9, x18, and x36 configurations
·Full data coherency providing most current data
·Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD [1]
·HSTL inputs and Variable drive HSTL output buffers
·Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
·Offered in both Pb-free and non Pb-free packages
·JTAG 1149.1 compatible test access port
·Delay Lock Loop (DLL) for accurate data placementSpecificationsStorage Temperature ................................. 65°C to +150°C
Ambient Temperature with Power Applied.. 55°C to +125°C
Supply Voltage on VDD Relative to GND........ 0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND....... 0.5V to +VDD
DC Applied to Outputs in High-Z ........ 0.5V to VDDQ + 0.3V
DC Input Voltage[14]..............................0.5V to VDD + 0.3V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch-up Current .................................................... >200 mADescriptionThe CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR-II architecture, QDR-II+ SRAMs consists of two separate ports to access the memory array. The Read Port has dedicated data outputs to support read operations and the Write Port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to "turn-around" the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II+ Read and Write Ports are completely independent of one another. In order to maximize data throughput, both Read and Write Ports of CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1561V18), 9-bit words (CY7C1576V18), 18-bit words (CY7C1563V18), or 36-bit words (CY7C1565V18) that burst sequentially into or out of the device.
Since data can be transferred into and out of theCY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus "turn-arounds".
Depth expansion of CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are accomplished with port selects for each port. Port selects allow each port to operate independently.
All synchronous inputs of CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
CY7C1565V18 Data Sheet
