CY7C1512

The CY7C1512 is a high-performance CMOS static RAM organizedas 65,536 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE₁), an active HIGH chip enable (CE₂), an active LOW output enable (OE), and three-state drivers. CY7C1512 has an automatic power- down feature that reduces power consumption by more than 75% when deselected.

Writing to the CY7C1512 is accomplished by taking chip enable one (CE₁) and write enable (WE) inputs LOW and chip enable two (CE₂) input HIGH. Data on the eight I/O pins (I/O0 through /O7) is then written into the location pecified on the address ins (A0 through A15).

Reading from the CY7C1512 is accomplished by taking chip enable ne (CE₁) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE₂) HIGH. Under hese conditions, the contents of the memory location specified y the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7)of CY7C1512 are placed in a igh-impedance state when the device is deselected (CE₁ IGH or CE₂ LOW), the outputs are disabled (OE HIGH), or uring a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).

The CY7C1512 is available in standard TSOP type I and 50-mil-wide plastic SOIC packages.