CY7C1475V25

The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs of  CY7C1471V25, CY7C1473V25 and CY7C1475V25 pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).

Write operations of  CY7C1471V25, CY7C1473V25 and CY7C1475V25 are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2,CE3) and an asynchronous Output Enable (OE) of   CY7C1471V25, CY7C1473V25 and CY7C1475V25 provide for easy bank sele tion and output tri-state control. In order to avoid bus  ontention, the output drivers are synchronously tri-stated during the data portion of a write sequence.