Features: •Pin-compatible and functionally equivalent to ZBT™
•Supports 250-MHz bus operations with zero wait states
-Available speed grades are 250, 200, and 167 MHz
•Internally self-timed output buffer control to eliminate the need to use asynchronous OE</a>
•Fully registered (inputs and outputs) for pipelined operation
•Byte Write capability
•Single 3.3V power supply
•3.3V/2.5V I/O power supply
•Fast clock-to-output time
-3.0 ns (for 250-MHz device)
-3.0 ns (for 200-MHz device)
-3.4 ns (for 167-MHz device)
•Clock Enable (CEN</a>) pin to suspend operation
•Synchronous self-timed writes
•CY7C1470V33 and CY7C1472V33 available in lead-free 100 TQFP, and 165-ball fBGA packages. CY7C1474V33 available in 209-ball fBGA package
•IEEE 1149.1 JTAG Boun dary Scan compatible
•Burst capability-linear or interleaved burst order
•"ZZ" Sleep Mode option and Stop Clock optionPinout
Specifications(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .............................65°C to +150°C
Ambient Temperature with
Power Applied.........................................55°C to +125°C
Supply Voltage on VDD Relative to GND........0.5V to +4.6V
DC to Outputs in Tri-State...................0.5V to VDDQ + 0.5V
DC Input Voltage...................................0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mADescriptionThe CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™)
logic, respectively.They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans-ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33,CY7C1472V33,and CY7C1474V33 are pin compatible and functionally equiv-alent to ZBT devices.
All synchronous inputs of CY7C1470V33, CY7C1472V33, and CY7C1474V33 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN</a>) signal,which when deasserted suspends operation and extends the previous clock cycle.
Write operations of CY7C1470V33, CY7C1472V33, and CY7C1474V33 are controlled by the Byte Write Selects(BW</a>aBW</a>h for CY7C1474V33, BW</a>aBW</a>d for CY7C1470V33and BW</a>aBW</a>b for CY7C1472V33) and a Write Enable (WE</a>)input. All writes are conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE</a>1, CE2, CE</a>3) and an asynchronous Output Enable (OE</a>) of CY7C1470V33, CY7C1472V33, and CY7C1474V33 provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
CY7C1472V33 Data Sheet
