Features: • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles• Can support up to 133-MHz bus operations with zero wait states - Data is transferred on every clock• Pin-compatible and functionally equivalent to ZBT™ devices...
CY7C1465AV25: Features: • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles• Can support up to 133-MHz bus operations with zero wait states - Data i...
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The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 are 2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV25/CY7C1463AV25/ CY7C1465AV25 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.
All synchronous inputs of CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations of CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence