CY7C1443AV25

The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25 are 2.5V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE₁), depth- expansion Chip Enables (CE₂ and CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_x, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables of CY7C1441AV25/CY7C1443AV25/CY7C1447AV25 are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1441AV25/CY7C1443AV25/CY7C1447AV25 operates from a +2.5V core power supply while all outputs may operate with either a +2.5V or 1.8V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.