Features: • Single 3.0V power supply• Ideal for low-voltage cache memory applications• High speed -12/15 ns• Low active power -198 mW (max.)• Low CMOS standby power (L) -165 mW (max.), f=fMAX• 2.0V data retention (L) -40 mW (max.)• Low-power alpha immune 6...
CY7C1399V: Features: • Single 3.0V power supply• Ideal for low-voltage cache memory applications• High speed -12/15 ns• Low active power -198 mW (max.)• Low CMOS standby power (L)...
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The CY7C1399V is a high-performance 3.0V CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.
An active LOW write enable signal (WE) of CY7C1399V controls the writing/ reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins.
The input/output pins of CY7C1399V remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. The CY7C1399V is available in standard 300-mil-wide SOJ and 28-pin TSOP type I packages