CY7C1386DV25

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3 ^[2] ), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Addresses and chip-enables of CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV).

Address, data inputs, and write controls of CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see Pin Definitions on page 6 and Truth Table [4, 5, 6, 7, 8, 9] on page 9 for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 operates from a +2.5V power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.